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1. "Exploiting Address Compression and Heterogeneous Interconnects for Efficient Message Management in Tiled CMPs"
   Antonio Flores, Manuel E. Acacio and Juan L. Aragón
   Journal of Systems Architecture,  vol. 56, no. 9, pp. 429-441, September 2010
   
   
2. "Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs"
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   IEEE Transactions on Computers, vol. 59, no. 1, pp. 16-28, January 2010
   
   
3. "An Energy Consumption Characterization of On-Chip Interconnection Networks for Tiled CMP Architectures"
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   The Journal of Supercomputing, vol. 45, no. 3, pp. 341-364, September 2008
   
   

   

4. "Energy-Efficient Hardware Prefetching for CMPs using Heterogeneous Interconnects"
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   In Proc. of the 18th Euromicro International Conference on Parallel, Distributed and Network-Based Computing (EUROMICRO-PDP), Pisa, Italy, February 2010
   
   
5. "Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs"
   Antonio Flores, Manuel E. Acacio and Juan L. Aragón
   In Proc. of the 37th IEEE Int. Conference on Parallel Processing (ICPP), Portland, OR, USA, September 2008
   
   
6. "Efficient Message Management in Tiled CMP Architectures using a Heterogeneous Interconnection Network"
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   Lecture Notes in Computer Science, vol. 4873, pp. 133-146, December 2007
   In Proc. of the 14th Int. Conference on High Performance Computing (HiPC), Goa, India, December 2007
   
   
7. "Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures"
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   In Proc. of the 4th IEEE Int. Symp. on Embedded Computing (SEC), Niagara Falls, Canada, May 2007
   
   

   

8. "Hardware Prefetching in Heterogeneous Interconnects: an Approach to Reducing Energy Consumption in Many-Core CMPs"
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   In Proc. of the XXI Jornadas de Paralelismo, Valencia (Spain), September 2010

9. "Power-Aware On-Chip Network Management in Tiled CMPs using Address Compression"
   Antonio Flores, Manuel E. Acacio and Juan L. Aragón
   In Proc. of the XIX Jornadas de Paralelismo, Castellón (Spain), September 2008
   
   
10. "Sim-PowerCMP: Un simulador de consumo para CMPs"
    Antonio Flores, Juan L. Aragón and Manuel E. Acacio
    In Proc. of the XVII Jornadas de Paralelismo, Albacete (Spain), September 2006
    
    

   

• "Improving the Performance and Reducing the Consumption of Multicore Processors using Heterogeneous Networks"
  Author: Antonio Flores Gil
  Advisors: Juan L. Aragón and Manuel E. Acacio
  University of Murcia (SPAIN) - September 24, 2010 
  
  The goal of this Thesis is reducing the global penalty associated to global intercore wires, in terms of both performance degradation and energy consumption, through the use of heterogeneous interconnects. 
  
  

        Last modified: September, 2010