Alberto Ros Bardisa

Biografía | Investigación | Estudiantes | Charlas | Herramientas y código | Docencia | Idioma

Soy Catedrático de Universidad del Departamento de Ingenería y Tecnología de Computadores de la Universidad de Murcia. Me licencié como Ingeniero en Informática en 2004 y me doctoré en 2009 por la misma universidad tras conseguir una beca FPU del Ministerio. He disfrutado de dos contratos postdoctorales en la Universidad Politécnica de Valencia y en la Universidad de Uppsala. En 2018 me concedieron un proyecto Consolidator Grant del European Research Council (ERC) para mejorar las prestaciones de los procesadores multicore. He publicado más de 100 artículos científicos en temas de coherencia de caché, diseños de la jerarquía de memoria, modelos de consistencia de memoria y microarquitectura del procesador. Fuí incluído en el Salón de la Fama del ISCA y del MICRO. Soy miembro senior de IEEE.

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General

• Alberto Ros, "Efficient and Scalable Cache Coherence for Chip Multiprocessors: Novel Proposals for Managing Cache Coherence in Future Many-Core Chip Multiprocessors", LAP Lambert Academic Publishing, febrero 2010. [url] [Entrada BibTeX]
• Alberto Ros, "Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors". Universidad de Murcia. Advisor: José Manuel García, Manuel Eugenio Acacio, septiembre 2009. [PDF] [Entrada BibTeX]

Predicción y pre-búsqueda

• Sebastian S. Kim, Alberto Ros, "Effective Context-Sensitive Memory Dependence Prediction". 30th Symposium on High Performance Computer Architecture (HPCA), págs. 515--527, Edimburgo, Escocia, marzo 2024. [PDF] [Entrada BibTeX]
• Alberto Ros, Alexandra Jimborean, "Wrong-Path-Aware Entangling Instruction Prefetcher". IEEE Transactions on Computers (TC), vol. 73 (2), págs. 548--559, febrero 2024. [PDF] [Entrada BibTeX]
• Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul Gratz, Daniel Jimenez, Samira Mirbagher-Ajorpaz, "Composite Instruction Prefetching: Combining Complementary Instruction Prefetchers". 40th IEEE International Conference on Computer Design (ICCD), págs. 471--478, Lake Tahoe, Nevada (EEUU), octubre 2022. [PDF] [Entrada BibTeX]
• Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, V. Viñals-Yúfera, Alberto Ros, "Berti: An Accurate Local-Delta Data Prefetcher". 55th International Symposium on Microarchitecture (MICRO), págs. 975--991, Chicago, Illinois (EEUU), octubre 2022. [PDF] [Entrada BibTeX]
• Alberto Ros, "BL∪E: A Timely, IP-based Data Prefetcher". The 1st ML-Based Data Prefetching Competition. ML for Computer Architecture and Systems, Evento a nivel mundial, junio 2021. [PDF] [Entrada BibTeX]
• Alberto Ros, Alexandra Jimborean, "A Cost-Effective Entangling Prefetcher for Instructions". 48th International Symposium on Computer Architecture (ISCA), págs. 99--111, Evento a nivel mundial, junio 2021. [PDF] [Entrada BibTeX]
• Alberto Ros, Alexandra Jimborean, "The Entangling Instruction Prefetcher". IEEE Computer Architecture Letters (CAL), vol. 19 (2), págs. 84--87, julio 2020. [PDF] [Entrada BibTeX]
• Alberto Ros, Alexandra Jimborean, "The Entangling Instruction Prefetcher". The 1st Instruction Prefetching Championship, Evento a nivel mundial, mayo 2020. [PDF] [Entrada BibTeX]
• Alberto Ros, "Berti: A Per-Page Best-Request-Time Delta Prefetcher". The 3rd Data Prefetching Championship, Phoenix, AZ (EEUU), junio 2019. [PDF] [Entrada BibTeX]

Paralelismo y memoria transaccional hardware

• Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "On the Interactions between ILP and TLP with Hardware Transactional Memory". Microprocessors and Microsystems (MICPRO), vol. 104, págs. 104975, febrero 2024. [PDF] [Entrada BibTeX]
• Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory". 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), págs. 157--164, Evento a nivel mundial, marzo 2022. [PDF] [Entrada BibTeX]
• Marina Shimchenko, Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, "Analysing Software Prefetching Opportunities in Hardware Transactional Memory". Journal of Supercomputing (SUPE), vol. 78 (1), págs. 919--944, enero 2022. [PDF] [Entrada BibTeX]
• Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros, "DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 33 (1), págs. 1--13, enero 2022. [PDF] [Entrada BibTeX]
• Eduardo José Gómez-Hernández, Rubén Titos-Gil, Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros, "Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations". 54th International Symposium on Microarchitecture (MICRO), págs. 337--349, Evento a nivel mundial, octubre 2021. [PDF] [Entrada BibTeX]
• Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "PfTouch: Concurrent Page-Fault Handling for Intel Restricted Transactional Memory". Journal of Parallel Distributed Computing (JPDC), vol. 145, págs. 111--123, noviembre 2020. [PDF] [Entrada BibTeX]
• Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Concurrent Irrevocability in Best-Effort Hardware Transactional Memory". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 31 (6), págs. 1301--1315, junio 2020. [PDF] [Entrada BibTeX]

Seguridad

• Christos Sakalis, Zamshed Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu, "Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation". 1st IEEE International Symposium on Secure and Private Execution Environment Design (SEED), págs. 89--100, Evento a nivel mundial, septiembre 2021. [PDF] [Entrada BibTeX]
• Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander, "Understanding Selective Delay as a Method for Efficient Secure Speculative Execution". IEEE Transactions on Computers (TC), vol. 69 (11), págs. 1584--1595, noviembre 2020. [PDF] [Entrada BibTeX]
• Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean, "Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design". 29th International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 241--254, Evento a nivel mundial, octubre 2020. [PDF] [Entrada BibTeX]
• Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander, "Efficient Invisible Speculative Execution through Selective Delay and Value Prediction". 46th International Symposium on Computer Architecture (ISCA), págs. 723--735, Phoenix, AZ (EEUU), junio 2019. [PDF] [Entrada BibTeX]
• Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander, "Ghost Loads: What is the Cost of Invisible Speculation?". ACM International Conference on Computing Frontiers, págs. 153--163, Alghero, Cerdeña, Italia, abril 2019. [PDF] [Entrada BibTeX]

Persistencia

• Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras, "TSOPER: Efficient Coherence-Based Strict Persistency". 12th Non-Volatile Memories Workshop (NVMW'21), University of California, San Diego, marzo 2021. [PDF] [Entrada BibTeX]
• Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras, "TSOPER: Efficient Coherence-Based Strict Persistency". 27th Symposium on High Performance Computer Architecture (HPCA), págs. 125--138, Evento a nivel mundial, febrero 2021. [PDF] [Entrada BibTeX]

Diseño de procesadores

• Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros, "Exploring Instruction Fusion Opportunities in General Purpose Processors". 55th International Symposium on Microarchitecture (MICRO), págs. 199--212, Chicago, Illinois (EEUU), octubre 2022. [PDF] [Entrada BibTeX]
• Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros, "Free Atomics: Hardware Atomic Operations without Fences". 49th International Symposium on Computer Architecture (ISCA), págs. 14--26, Nueva York, Nueva York (EEUU), junio 2022. [PDF] [Entrada BibTeX]
• Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros, "Boosting Store Buffer Efficiency with Store-Prefetch Bursts". 53rd International Symposium on Microarchitecture (MICRO), págs. 568--580, Evento a nivel mundial, octubre 2020. [PDF] [Entrada BibTeX]
• Ricardo Alves, Alberto Ros, David Black-Schaffer, Stefanos Kaxiras, "Filter Caching for Free: The Untapped Potential of the Store Buffer". 46th International Symposium on Computer Architecture (ISCA), págs. 436--448, Phoenix, AZ (EEUU), junio 2019. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "The Superfluous Load Queue". 51st International Symposium on Microarchitecture (MICRO), págs. 95--107, Fukuoka, Japón, octubre 2018. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "Non-Speculative Store Coalescing in Total Store Order". 45th International Symposium on Computer Architecture (ISCA), págs. 221--234, Los Ángeles, California (EEUU), junio 2018. [PDF] [Entrada BibTeX]
• Stefanos Kaxiras, Trevor E. Carlson, Mehdi Alipour, Alberto Ros, "Non-Speculative Load Reordering in TSO". IEEE Micro (TopPicks), vol. 38 (3), págs. 48--57, mayo 2018. [PDF] [Entrada BibTeX]
• Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras, "Non-Speculative Load-Load Reordering in TSO". 44th International Symposium on Computer Architecture (ISCA), págs. 187--200, Toronto, Ontario (Canadá), junio 2017. [PDF] [Entrada BibTeX]

Consistencia de memoria y coherencia sensible al modelo de consistencia

• Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras, "Speculative Inter-Thread Store-to-Load Forwarding in SMT Architectures". Journal of Parallel Distributed Computing (JPDC), vol. 173, págs. 94--106, marzo 2023. [PDF] [Entrada BibTeX]
• Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras, "ITSLF: Inter-Thread Store-to-Load Forwarding in Simultaneous Multithreading". 54th International Symposium on Microarchitecture (MICRO), págs. 1296--1308, Evento a nivel mundial, octubre 2021. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "Speculative Enforcement of Store Atomicity". 53rd International Symposium on Microarchitecture (MICRO), págs. 555--567, Evento a nivel mundial, octubre 2020. [PDF] [Entrada BibTeX]
• Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras, "Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28 (12), págs. 3413--3425, diciembre 2017. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "Racer: TSO Consistency via Race Detection". 49th International Symposium on Microarchitecture (MICRO), págs. 1--13, Taipei, Taiwan, octubre 2016. [PDF] [Entrada BibTeX]
• Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras, "POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics". 25th International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 433--434, Haifa (Israel), septiembre 2016. [PDF] [Entrada BibTeX]
• Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras, "Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead". ACM Transactions on Architecture and Code Optimization (TACO), vol. 13 (1), págs. 1:1--1:22, marzo 2016. [PDF] [Entrada BibTeX]
• Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras, "An Efficient, Self-Contained, On-Chip, Directory: DIR1-SISD". 24th International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 317--330, San Francisco, California (EEUU), octubre 2015. [PDF] [Entrada BibTeX]
• Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras, "The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence". ACM Transactions on Architecture and Code Optimization (TACO), vol. 12 (3), págs. 26:1--26:21, agosto 2015. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "Callback: Efficient Synchronization without Invalidation with a Directory Just for Spin-Waiting". 42nd International Symposium on Computer Architecture (ISCA), págs. 427--438, Portland, Oregón (EEUU), junio 2015. [PDF] [Entrada BibTeX]
• Alberto Ros, Mahdad Davari, Stefanos Kaxiras, "Hierarchical Private/Shared Classification: the Key to Simple and Efficient Coherence for Clustered Cache Hierarchies". 21st Symposium on High Performance Computer Architecture (HPCA), págs. 186--197, Bay area, California (EEUU), febrero 2015. [PDF] [Entrada BibTeX]
• Stefanos Kaxiras, Alberto Ros, "A New Perspective for Efficient Virtual-Cache Coherence". 40th International Symposium on Computer Architecture (ISCA), págs. 535--547, Tel-Aviv (Israel), junio 2013. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "Complexity-Effective Multicore Coherence". 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 241--252, Minneapolis, MN (EEUU), septiembre 2012. [PDF] [Entrada BibTeX]
• Stefanos Kaxiras, Alberto Ros, "Efficient, Snoopless, System-on-Chip Coherence". 25th IEEE International System-on-Chip Conference (IEEE SOCC), págs. 230--235, Cataratas del Niágara, Nueva York (EEUU), septiembre 2012. [PDF] [Entrada BibTeX]

Codiseño software-hardware

• Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros, "CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions". 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 1--13, Viena, Austria, octubre 2023. [PDF] [Entrada BibTeX]
• Juan Manuel Cebrian, Thibaud Balem, Adrian Barredo, Marc Casas, Miquel Moreto, Alberto Ros, Alexandra Jimborean, "Compiler-Assisted Compaction/Restoration of SIMD Instructions". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 33 (4), págs. 779--791, abril 2022. [PDF] [Entrada BibTeX]
• Sawan Singh, Alexandra Jimborean, Alberto Ros, "Regional Out-of-Order Writes in Total Store Order". 29th International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 205--216, Evento a nivel mundial, octubre 2020. [PDF] [Entrada BibTeX]
• Alexandra Jimborean, Per Ekemark, Jonatan Waern, Stefanos Kaxiras, Alberto Ros, "Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 29 (3), págs. 527--541, marzo 2018. [PDF] [Entrada BibTeX]
• Alexandra Jimborean, Jonatan Waern, Per Ekemark, Stefanos Kaxiras, Alberto Ros, "Automatic Detection of Extended Data-Race-Free Regions". 15th International Symposium on Code Generation and Optimization (CGO), págs. 14--26, Austin, Texas (EEUU), febrero 2017. [PDF] [Entrada BibTeX]
• Alberto Ros, Alexandra Jimborean, "A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27 (11), págs. 3101--3115, noviembre 2016. [PDF] [Entrada BibTeX]
• Alberto Ros, Alexandra Jimborean, "A Dual-Consistency Cache Coherence Protocol". 29th International Parallel & Distributed Processing Symposium (IPDPS), págs. 1119--1128, Hyderabad (India), mayo 2015. [PDF] [Entrada BibTeX]

Verificación de protocolos de coherencia de cachés

• Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu, "Mending Fences with Self-Invalidation and Self-Downgrade". Logical Methods in Computer Science (LMCS), vol. 14 (1), págs. 1--33, enero 2018. [PDF] [Entrada BibTeX]
• Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu, "Fencing Programs with Self-Invalidation and Self-Downgrade". International Conference, FORTE 2016, Held as Part of the 11th International Federated Conference on Distributed Computing Techniques, DisCoTec 2016, págs. 19--35, Heraclión (Creta), junio 2016. [PDF] [Entrada BibTeX]

Argo: Memory compartida distribuida

• Stefanos Kaxiras, David Klaftenegger, Magnus Norgren, Alberto Ros, Konstantinos Sagonas, "Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory". 24th International Symposium on High-Performance Parallel and Distributed Computing (HPDC), págs. 3--14, Portland, Oregón (EEUU), junio 2015. [PDF] [Entrada BibTeX]

Classificación de datos y accesos

• Bhargavi R. Upadhyay, Alberto Ros, Supriya M., "Fine-Grain Data Classification to Filter Token Coherence Traffic". Journal of Parallel Distributed Computing (JPDC), vol. 171, págs. 40--53, enero 2023. [PDF] [Entrada BibTeX]
• Bhargavi R. Upadhyay, Alberto Ros, Jalpa Shah, "Efficient Classification of Private Memory Blocks". Journal of Parallel Distributed Computing (JPDC), vol. 157, págs. 256--268, noviembre 2021. [PDF] [Entrada BibTeX]
• Bhargavi R. Upadhyay, Alberto Ros, Murty NS, "TLB-based Block-Grain Classification of Private Data". 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), págs. 122--130, Vasteras, Suecia, marzo 2020. [PDF] [Entrada BibTeX]
• Albert Esteve, Alberto Ros, Antonio Robles, María E. Gómez, "TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 29 (5), págs. 1188--1201, mayo 2018. [PDF] [Entrada BibTeX]
• Albert Esteve, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28 (8), págs. 2401--2413, agosto 2017. [PDF] [Entrada BibTeX]
• Albert Esteve, Alberto Ros, Antonio Robles, María E. Gómez, José Duato, "TokenTLB: A Token-Based Page Classification Approach". International Conference on Supercomputing (ICS), págs. 26:1--26:13, Estambul (Turquía), junio 2016. [PDF] [Entrada BibTeX]
• Albert Esteve, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27 (3), págs. 748--761, marzo 2016. [PDF] [Entrada BibTeX]
• Alberto Ros, Blas Cuesta, María E. Gómez, Antonio Robles, José Duato, "Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors". 42nd International Conference on Parallel Processing (ICPP), págs. 562--571, Lyon (Francia), octubre 2013. [PDF] [Entrada BibTeX]

Cachés separadas para datos privados y compartidos

• Juan M. Cebrian, Ricardo Fernández-Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros, "A Dedicated Private-Shared Cache Design for Scalable Multiprocessors". Concurrency and Computation: Practice and Experience (CPE), vol. 29 (2), enero 2017. [PDF] [Entrada BibTeX]
• Juan M. Cebrian, Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, "Early Experiences with Separate Caches for Private and Shared Data". 1st Workshop on E-science ReseaRch leading tO negative Results (ERROR), págs. 572--579, Munich (Alemania), septiembre 2015. [PDF] [Entrada BibTeX]

Protocolos de coherencia basados en listas

• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence". International Conference on Architecture of Computing Systems (ARCS), págs. 100--112, Nuremberg (Alemania), abril 2016. [PDF] [Entrada BibTeX]
• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Are Distributed Sharing Codes a Solution to the Scalability Problem of Coherence Directories in Manycores? An Evaluation Study". Journal of Supercomputing (SUPE), vol. 72 (2), págs. 612--638, febrero 2016. [PDF] [Entrada BibTeX]
• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs". 3rd Workshop on On-Chip Memory Hierarchies and Interconnects (OMHI), págs. 254--265, Oporto (Portugal), agosto 2014. [PDF] [Entrada BibTeX]

Cachés eficientes

• Joan J. Valls, Alberto Ros, María E. Gómez, Julio Sahuquillo, "The Tag Filter Architecture: An Energy-Efficient Cache and Directory Design". Journal of Parallel Distributed Computing (JPDC), vol. 100 (2), págs. 193--202, febrero 2017. [PDF] [Entrada BibTeX]
• Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García, "Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses". IEEE Transactions on Computers (TC), vol. 64 (6), págs. 1534--1547, junio 2015. [PDF] [Entrada BibTeX]
• Joan J. Valls, Julio Sahuquillo, Alberto Ros, María E. Gómez, "The Tag Filter Cache: An Energy-Efficient Approach". 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), págs. 182--189, Turku (Finlandia), marzo 2015. [PDF] [Entrada BibTeX]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "PS-Cache: An Energy-Efficient Cache Design for Chip Multiprocessors". Journal of Supercomputing (SUPE), vol. 71 (1), págs. 67--86, enero 2015. [PDF] [Entrada BibTeX]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "PS-Cache: An Energy-Efficient Cache Design for Chip Multiprocessors". 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 407, Edimburgo (Escocia), septiembre 2013. [PDF] [Entrada BibTeX]
• Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García, "ASCIB: Adaptive Selection of Cache Indexing Bits for Reducing Conflict Misses". International Symposium on Low Power Electronics and Design (ISLPED), págs. 51--56, Redondo Beach, California (EEUU), julio 2012. [PDF] [Entrada BibTeX]

Desactivación de la coherencia

• Blas Cuesta, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Non-Coherent Memory Blocks". IEEE Transactions on Computers (TC), vol. 62 (3), págs. 482--495, marzo 2013. [PDF] [Entrada BibTeX]
• Blas Cuesta, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks". 38th International Symposium on Computer Architecture (ISCA), págs. 93--103, San Jose, California (EEUU), junio 2011. [PDF] [Entrada BibTeX]

Políticas de mapeo a cachés compartidas ditribuidas

• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "DAPSCO: Distance-Aware Partially Shared Cache Organization". ACM Transactions on Architecture and Code Optimization (TACO), vol. 8 (4), págs. 25:1--25:19, enero 2012. [PDF] [Entrada BibTeX]
• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "DAPSCO: Distance-Aware Partially Shared Cache Organization". 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), págs. 25:1--25:19, París (Francia), enero 2012. [PDF] [Entrada BibTeX]
• Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García, "Distance-Aware Round-Robin Mapping for Large NUCA Caches". 16th International Conference on High Performance Computing (HiPC), págs. 79--88, Cochin (India), diciembre 2009. [PDF] [Entrada BibTeX]

Extension de protocolos de coherencia

• Alberto Ros, Blas Cuesta, María E. Gómez, Antonio Robles, José Duato, "Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems". 4th International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2), págs. 691--696, Madrid (España), julio 2012. [PDF] [Entrada BibTeX]
• Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, Maria E. Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato, "Extending Magny-Cours Cache Coherence". IEEE Transactions on Computers (TC), vol. 61 (5), págs. 593--606, mayo 2012. [PDF] [Entrada BibTeX]
• Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, María E. Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato, "EMC²: Extending Magny-Cours Coherence for Large-Scale Servers". 17th International Conference on High Performance Computing (HiPC), págs. 1--10, Goa (India), diciembre 2010. [PDF] [Entrada BibTeX]

Protocolos de coherencia sin indirección

• José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio, "Photonic-Based Express Coherence Notications for Many-core CMPs". Journal of Parallel Distributed Computing (JPDC), vol. 113, págs. 179--194, marzo 2018. [PDF] [Entrada BibTeX]
• José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio, "ECONO: Express Coherence Notifications for Efficient Cache Coherency in Many-Core CMPs". XIII International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), págs. 237--244, Samos (Grecia), julio 2013. [PDF] [Entrada BibTeX]
• José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio, "Efficient Dir0B Cache Coherency for Many-Core CMPs". 18th International Conference on Computational Science (ICCS), págs. 2545--2548, Barcelona (España), junio 2013. [Entrada BibTeX]
• Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, "Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs". 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), págs. 43--50, Columbia University, Nueva York (EEUU), octubre 2012. [PDF] [Entrada BibTeX]
• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation". 40th International Conference on Parallel Processing (ICPP), págs. 51--62, Taipei (Taiwan), septiembre 2011. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "A Direct Coherence Protocol for Many-Core Chip Multiprocessors". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 21 (12), págs. 1779--1792, diciembre 2010. [PDF] [Entrada BibTeX]
• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "Exploring the Field of Cache Coherence Protocols For Server Consolidation". 6th HiPEAC Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), págs. 211--214, Terrasa (España), julio 2010. [PDF] [Entrada BibTeX]
• Alberto Ros, "Parallel and Distributing Computing", IN-TECH, enero 2010. [url] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, Cache Coherence Protocols for Many-Core CMPs, "Parallel and Distributing Computing", IN-TECH, págs. 93--118, enero 2010. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs". 8th International Conference on Advanced Parallel Processing Technologies (APPT), págs. 11--27, Rapperswil (Suiza), agosto 2009. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "DiCo-CMP: Efficient Cache Coherency in Tiled CMP Architectures". 22nd International Parallel & Distributed Processing Symposium (IPDPS), págs. 1--11, Miami, Florida (EEUU), abril 2008. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors". 14th International Conference on High Performance Computing (HiPC), págs. 147--160, Goa (India), diciembre 2007. [PDF] [Entrada BibTeX]

Cachés de directorio escalables

• Rubén Titos-Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio, "Way Combination for an Adaptive and Scalable Coherence Directory". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 30 (11), págs. 2608--2623, noviembre 2019. [PDF] [Entrada BibTeX]
• Rubén Titos-Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Way-Combining Directory: An Adaptive and Scalable Low-Cost Coherence Directory". International Conference on Supercomputing (ICS), págs. 20:1--20:10, Chicago, Illinois (EEUU), junio 2017. [PDF] [Entrada BibTeX]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "A Directory Cache with Dynamic Private-Shared Partitioning". 23rd International Conference on High Performance Computing (HiPC), págs. 382--391, Hyderabad (India), diciembre 2016. [PDF] [Entrada BibTeX]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "PS Directory: A Scalable Multilevel Directory Cache for CMPs". Journal of Supercomputing (SUPE), vol. 71 (8), págs. 2847--2876, agosto 2015. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, "DASC-DIR: A Low-Overhead Coherence Directory for Many-Core Processors". Journal of Supercomputing (SUPE), vol. 71 (3), págs. 781--807, marzo 2015. [PDF] [Entrada BibTeX]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, José Duato, "PS-Dir: A Scalable Two-Level Directory Cache". 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), págs. 451--452, Minneapolis, MN (EEUU), septiembre 2012. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "A Scalable Organization for Distributed Directories". Journal of Systems Architecture (JSA), vol. 56 (2-3), págs. 77--87, marzo 2010. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, "Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs". 4th Workshop on Highly Parallel Processing on a Chip (HPPC), págs. 87--97, Ischia (Italia), agosto 2010. [PDF] [Entrada BibTeX]
• Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, José M. García, "Two Proposals for the Inclusion of Directory Information in the Last-Level Private Caches of Glueless Shared-Memory Multiprocessors". Journal of Parallel Distributed Computing (JPDC), vol. 68 (11), págs. 1413--1424, noviembre 2008. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "Scalable Directory Organization for Tiled CMP Architectures". International Conference on Computer Design (CDES), págs. 112--118, Las Vegas, Nevada (EEUU), julio 2008. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors". ACM International Conference on Computing Frontiers, págs. 321--330, Ischia (Italia), mayo 2006. [PDF] [Entrada BibTeX]
• Alberto Ros, Manuel E. Acacio, José M. García, "A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors". 11th International Euro-Par Conference, págs. 582--591, Lisboa (Portugal), agosto 2005. [PDF] [Entrada BibTeX]

Evaluación de protocolos de coherencia

• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "To Be Silent or Not: On the Impact of Evictions of Clean Data in Cache-Coherent Multicores". Journal of Supercomputing (SUPE), vol. 73 (10), págs. 4428--4443, octubre 2017. [PDF] [Entrada BibTeX]

Simulación

• Josué Feliu, Arthur Perais, Daniel Jimenez, Alberto Ros, "Rebasing Microarchitectural Research with Industry Traces". 2023 IEEE International Symposium on Workload Characterization (IISWC), págs. 100--114, Gante, Bélgica, octubre 2023. [PDF] [Entrada BibTeX]
• Emilio Dominguez-Sanchez, Alberto Ros, "MBPlib: Modular Branch Prediction Library". International Symposium on Performance Analysis of Systems and Software (ISPASS), págs. 71--80, Raleigh, Carolina del Norte (EEUU), abril 2023. [PDF] [Entrada BibTeX]
• Eduardo José Gómez-Hernández, Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros, "Splash-4: A Modern Benchmark Suite with Lock-Free Constructs". 2022 IEEE International Symposium on Workload Characterization (IISWC), págs. 51--64, Austin, Texas (EEUU), noviembre 2022. [PDF] [Entrada BibTeX]
• Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros, "Splash-4: Improving Scalability with Lock-Free Constructs". International Symposium on Performance Analysis of Systems and Software (ISPASS), págs. 235--236, Evento a nivel mundial, marzo 2021. [PDF] [Entrada BibTeX]
• Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras, Alberto Ros, "Splash-3: A Properly Synchronized Benchmark Suite for Contemporary Research". International Symposium on Performance Analysis of Systems and Software (ISPASS), págs. 101--111, Uppsala (Suecia), abril 2016. [PDF] [Entrada BibTeX]
• Alberto Ros, Stefanos Kaxiras, "Fast&Furious: A Tool for Detecting Covert Racing". 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA) and 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (DITAM), págs. 1--6, Amsterdam (Países Bajos), enero 2015. [PDF] [Entrada BibTeX]
• Francisco Triviño, Francisco J. Andujar, José L. Sánchez, Francisco J. Alfaro, Alberto Ros, "Self-Related Traces: An Alternative to Full-System Simulation for Networks-On-Chip". International Conference on High Performance Computing & Simulation (HPCS), págs. 819--824, Estambul (Turquía), julio 2011. [PDF] [Entrada BibTeX]