@InProceedings{ssingh-micro26,
  author =       {Simranjit Singh and Agust{\'{\i}}n Navarro-Torres and Biswabandan Panda and Alberto Ros},
  title =        {Rebasing and Optimizing Cache Miss Handling: Fetching Beyond MSHR Capacity},
  booktitle =    {59th International Symposium on Microarchitecture (MICRO)},
  doi =          {10.1109/MICRO67795.2026.00062},
  pages =        {723--737},
  year =         {2026},
  editor =       {ACM/IEEE},
  address =      {Athens (Grecia)},
  month =        nov,
  publisher =    {IEEE Computer Society},
  ratio-acep =   {25.30% (213/842)},
  isbn =         {979-8-3195-4767-5},
  issn =         {2379-3155},
  url =          {http://webs.um.es/aros/papers/pdfs/ssingh-micro26.pdf}
}