**Biography**

Juan M. Cebrian is author of two books, 23 JCR journals (11 as first author, of which 5 are Q1 and of these, 4 are D1), and 27 conferences (5 CORE/GGS A and 4 CORE/GGS A+). I've always been directly involved in the development of all my publications, being first or second author of most of them. Internationalization has always been key in my professional career. In 15 of my 23 JCR journals and in 21 of my 26 conferences there are international contributors (36 out of 49 73%). In addition, I've presented my work at 25 conferences, published 3 newsletter articles and several posters in the HiPEAC network of excellence, organized a workshop in vector computing, invited to three international talks, conducted interviews on radio and newspapers, showing my interest in disseminating results to both experts and the general public. Co-director of 3 Master Theses (1 international) and 5 Doctoral Theses (1 international, 2 in progress). Other quality indicators include 4 HiPEAC awards, a total readership in Research Gate of 7811, 461 citations in Google Scholar, an h-index of 13 and an i-index of 17.

My collaboration with the international community is not limited to publications, I have also reviewed more than 100 articles for international conferences and journals (including CORE/GGS A and A+ and JCR-1) as well as evaluated numerous international Master's theses and final projects. In the last two years I've been program committee member for IPDPS, ISPASS, ADAPT and PACT and HPCA conferences. I've also contributed to the community with the ParVec benchmark suite, which includes a multi-platform library for unified SIMD coding (NEON, SSE, AVX and AVX512) and a vector math library, a PAPI consumer module for ODROID-XU boards, a semi-automatic simulation infrastructure verification tool and several patches for the gem5 simulator. I also was a collaborator in the development of the protein folding application BINDSURF.

My first experience leading research lines was in vector processing (SIMD) for the NTNU EECS project, which included the development of vectorized applications, evaluation of energy efficiency and temperature, and SIMD compression techniques for bandwidth improvement. It was also my first collaboration with companies, i.e., Powel, a company that distributes water and electricity in Norway and uses his proposals (NDA). It was also my first Ph.D. Thesis direction (Abdullah Al Hasib). The knowledge of SIMD compression allowed Hasib to get his first job at Appear TV.
At ROMOL project, I led a small group of BSC researchers who developed a compiler as well as the necessary support in the gem5 simulator to handle variable register size vector architectures (supports Intel's SSE, AVX and AVX512) during 18 months of development (2+ million lines of code). This Infrastructure has been used in at least 3 CORE A+ releases (MICRO and HPCA). In two of them, I am not a co-author, but shared the simulator. At the same time, arm released the SVE specification, given the similarity of the work, I joined the Montblanc project to collaborate in the evaluation and improvement of the architecture in my second collaboration with companies (NDA). Two of my co-directed Master Thesis (Helena Caminal and Adrián Barredo) are associated with these projects. Caminal continued her Ph.D. in the United States. I co-directed Barredo, who completed his Ph.D. and is currently working for Huawei. In parallel, I maintained my collaborations with NTNU (co-directed Master Thesis -Christian De Frene-) and the University of Murcia (co-directed Doctoral Thesis -Mario Hernandez-). Hernández is currently working as a professor at the Universidad Autónoma de Guerrero. Part of the results of this work have been presented in a talk invited by another co-author at CERN.

I am currently leading a line of research in prefetching within the ECHO project [2] and am co-director of doctoral students in non-speculative atomic execution. Two of the works performed for this project have been patented. In addition, I collaborate with NTNU and SINTEF in the BAMPAM project, developing an FFT accelerator in FPGA that has been prototyped in two companies, an oil company and a railway network management company in preventive maintenance in industry 4.0 (NDA).

**My Skillset includes**
Software: Java, C, C++, MS-Office, UNIX Shell Programming, Pascal, ORACLE, SQL Server, SIMD programming with intrinsics (SSE, AVX and NEON), Basic CUDA, OpenMP, OmpSs and OpenCL knowledge.
Tools: Simplescalar, Wattch, Hotspot, HotLeakage, McPAT, GEMS, Opal, Simics, MATLAB, emacs, vi, PSPICE (basic designs).

**Teaching**
The candidate has completed a total of 48.84 credits in teaching activities.
The main courses he has been involved in are: System Administration (3rd Year) in 2009/2010 and 2010/2011, and Advanced Computer Structure (2nd Year) in 2019/2020, 2020/2021, 2021/2022, 2022/2023, and 2023/2024.
Currently teaching Computer Organization (3rd year), Distributed Systems (4th year), Parallel and Distributed Systems (3rd year), and Advanced Operating System Administration (4th year) during 2024/2025