Research interests
My research efforts are currently focused on computer
architecture; however, my interests span many aspects of computer
systems research (including networking, compilers, system
software, and parallel programming). Specifically, my current
research interests include multiprocessor and multi-core memory
systems, efficient cache coherence protocols, hardware fault
tolerance, hardware transactional memory systems, and efficient
synchronization primitives.Click here to take a look at my CV
INVITED TALKS
- "Meltdown and Spectre Vulnerabilities: Causes, Risks and
Possible Solutions". Facultad de Informática, Universidad de
Murcia, Feb. 16th, 2018.
- “Increased Hardware Support for Efficient Communication and
Synchronization in Future Manycores”. Keynote at OMHI 2014,
August 26th, 2014.
- "Efficient Communication and Synchronization in Many-Core
CMPs". Dpto. Arquitectura de Computadores, Universidad de
Málaga, July 6th, 2012.
PUBLICATION list (dblp)
pHD THESIS
Title: “Improving the Performance and Scalability of Directory-based Shared-Memory Multiprocessors”Author: Manuel E. Acacio
Advisors: José Duato (UPV), José Manuel García (UM) and José González (Intel Barcelona Labs)
Defended on March 26, 2003
Awarded with the Best Ph.D. Thesis Prize. Facultad de Informática. Universidad de Murcia. January 2004.
PHD STUDENTS
Current Students- Francisco Muñoz-Martínez. “Customized Hardware for Efficient Deep Neural Network Support”. Co-advised with José L. Abellán.
- Ricardo Fernández-Pascual, Ph.D. July 2009, "Fault-tolerant cache coherence protocols for CMPs" (co-advised with José M. García).
- Alberto Ros, Ph.D. September 2009, "Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors" (co-advised with José M. García).
- Antonio Flores. Ph.D. September 2010, "Improving the Performance and Reducing the Consumption of Multicore Processors using Heterogeneous Networks". Co-advised with Juan L. Aragón.
- Rubén Titos-Gil. Ph.D. November 2011. "Hardware Techniques for High-Performance Transactional Memory in Many-Core Chip Multiprocessors".
- José L. Abellán. December 2012. "Efficient Communication and Synchronization in Many-Core CMPs". Co-advised with Juan Fernández.
- Epifanio Gaona. January 2016. "Efficient Hardware Transactional Memory Systems". Co-advised with Juan Fernández.