Research interests
My research efforts are currently focused on computer
architecture; however, my interests span many aspects of computer
systems research (including networking, compilers, system
software, and parallel programming). Specifically, my current
research interests include multiprocessor and multi-core memory
systems, efficient cache coherence protocols, hardware fault
tolerance, hardware transactional memory systems, efficient
synchronization primitives and accelerator architectures for DL.Publication list
2026
- Nicolás Meseguer, Daoxuan Xu, Yifan Sun, Michael Pellauer, José L. Abellán, Manuel E. Acacio. QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs.. HPCA : 1-14.
2025
- Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros. WoperTM: Got Nacks? Use Them!. IEEE Comput. Archit. Lett. : 157-160.
- Joaquín Ferrer, Juan M. Cebrian, Ricardo Fernández-Pascual, Manuel E. Acacio. Precise characterization of coherence activity in multicores using gem5.. J. Supercomput. : 935.
- Nicolás Meseguer, Yifan Sun, Michael Pellauer, José L. Abellán, Manuel E. Acacio. ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs.. GPGPU@PPoPP : 21-27.
- Ashkan Asgharzadeh, Josué Feliu, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros. No Rush in Executing Atomic Instructions.. HPCA : 1618-1630.
- Adrián Navarro, José Cano, José L. Abellán, Manuel E. Acacio. QuFi: Adaptive Tiled Gustavson Output Reuse for Edge Sparse DNN Accelerators.. ICCD : 119-126.
2024
- Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. On the interactions between ILP and TLP with hardware transactional memory.. Microprocess. Microsystems : 104975.
- Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros. Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory.. MICRO : 840-855.
2023
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna. STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators.. ACM J. Emerg. Technol. Comput. Syst. : 32:1-32:20.
- Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras. Speculative inter-thread store-to-load forwarding in SMT architectures.. J. Parallel Distributed Comput. : 94-106.
- Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions.. PACT : 1-13.
- Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna. Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.. ASPLOS (3) : 252-265.
- Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, Tushar Krishna. Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.. CoRR.
2022
- Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean. Analysing software prefetching opportunities in hardware transactional memory.. J. Supercomput. : 919-944.
- J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.. IEEE Trans. Parallel Distributed Syst. : 1-13.
- Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna. Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators.. IPDPS : 571-582.
- Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.. PDP : 157-164.
2021
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators.. IEEE Comput. Archit. Lett. : 122-125.
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators.. IISWC : 201-213.
- Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras. ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading.. MICRO : 1296-1308.
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna. A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators.. NOCS : 1-8.
- Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna. A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators.. CoRR.
2020
- J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. PfTouch: Concurrent page-fault handling for Intel restricted transactional memory.. J. Parallel Distributed Comput. : 111-123.
- Labiba Gillani Fahad, Syed Fahad Tahir, Waseem Shahzad, Mehdi Hassan, Hani Alquhayz, Rabia Hassan, Manuel E. Acacio Sanchez. Ant Colony Optimization-Based Streaming Feature Selection: An Application to the Medical Image Diagnosis.. Sci. Program. : 1064934:1-1064934:10.
- Brian Broll, Umesh Timalsina, Péter Völgyesi, Tamás Budavári, Ákos Lédeczi, Manuel E. Acacio Sanchez. A Machine Learning Gateway for Scientific Workflow Design.. Sci. Program. : 8867380:1-8867380:15.
- J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.. IEEE Trans. Parallel Distributed Syst. : 1301-1315.
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna. STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators.. CoRR.
2019–1999
- Manuel E. Acacio, Julio Sahuquillo. Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems.. Concurr. Comput. Pract. Exp..
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio. InsideNet: A tool for characterizing convolutional neural networks.. Future Gener. Comput. Syst. : 298-315.
- J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio. Way Combination for an Adaptive and Scalable Coherence Directory.. IEEE Trans. Parallel Distributed Syst. : 2608-2623.
- Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio. CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators.. Euro-Par Workshops : 720-724.
- José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio. Photonic-based express coherence notifications for many-core CMPs.. J. Parallel Distributed Comput. : 179-194.
- Gregorio Bernabé, Manuel E. Acacio. On the Parallelization of Stream Compaction on a Low-Cost SDC Cluster.. Sci. Program. : 2037272:1-2037272:10.
- Gregorio Bernabé, Raúl Hernández, Manuel E. Acacio. Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster.. J. Supercomput. : 1765-1778.
- Francisco Muñoz-Martínez, Manuel E. Acacio. SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors.. PDP : 344-347.
- Juan M. Cebrian, Ricardo Fernández-Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros. A dedicated private-shared cache design for scalable multiprocessors.. Concurr. Comput. Pract. Exp..
- Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.. J. Supercomput. : 4428-4443.
- J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. Way-combining directory: an adaptive and scalable low-cost coherence directory.. ICS : 20:1-20:10.
- Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study.. J. Supercomput. : 612-638.
- Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence.. ARCS : 100-112.
- Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García. Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses.. IEEE Trans. Computers : 1534-1547.
- Alberto Ros, Manuel E. Acacio. DASC-DIR: a low-overhead coherence directory for many-core processors.. J. Supercomput. : 781-807.
- Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio. Fast and efficient commits for Lazy-Lazy hardware transactional memory.. J. Supercomput. : 4305-4326.
- Juan M. Cebrian, Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio. Early Experiences with Separate Caches for Private and Shared Data.. e-Science : 572-579.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. Efficient Hardware-Supported Synchronization Mechanisms for Manycores.. Handbook on Data Centers : 753-803.
- J. Rubén Titos Gil, Manuel E. Acacio. Hardware Approaches to Transactional Memory in Chip Multiprocessors.. Handbook on Data Centers : 805-835.
- Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio. Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems.. J. Supercomput. : 914-934.
- J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström. ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory.. IEEE Trans. Parallel Distributed Syst. : 1359-1369.
- Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio. Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.. Euro-Par Workshops (2) : 254-265.
- Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio. On the design of energy-efficient hardware transactional memory systems.. Concurr. Comput. Pract. Exp. : 862-880.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. Design of an efficient communication infrastructure for highly contended locks in many-core CMPs.. J. Parallel Distributed Comput. : 972-985.
- J. Rubén Titos Gil, Manuel E. Acacio, José M. García. Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory.. IEEE Trans. Parallel Distributed Syst. : 59-71.
- J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström. Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory.. IEEE Trans. Parallel Distributed Syst. : 2192-2201.
- Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández. Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory.. ARCS : 220-231.
- Mario Lodde, José Flich, Manuel E. Acacio. Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support.. Euro-Par : 178-190.
- José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio. Efficient Dir0B Cache Coherency for Many-Core CMPs.. ICCS : 2545-2548.
- José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio. ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.. ICSAMOS : 237-244.
- J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero. Hardware transactional memory with software-defined conflicts.. ACM Trans. Archit. Code Optim. : 31:1-31:20.
- Alberto Ros, Blas Cuesta Saez, Ricardo Fernández-Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato. Extending Magny-Cours Cache Coherence.. IEEE Trans. Computers : 593-606.
- José M. Cecilia, José L. Abellán, Juan Fernández, Manuel E. Acacio, José M. García, Manuel Ujaldon. Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE.. J. Supercomput. : 787-803.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. Efficient Hardware Barrier Synchronization in Many-Core CMPs.. IEEE Trans. Parallel Distributed Syst. : 1453-1466.
- José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini. Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.. DATE : 491-496.
- Mario Lodde, José Flich, Manuel E. Acacio. Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols.. Euro-Par : 206-218.
- Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.. HPCA : 141-152.
- Manuel E. Acacio, Javier Cuenca, Lorenzo Fernández Maimó, Ricardo Fernández-Pascual, Joaquín Cervera, Domingo Giménez, M. Carmen Garrido, Juan A. Sánchez-Laguna, José Guillén, Juan Alejandro Palomino Benito, María-Eugenia Requena. An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain.. IPDPS Workshops : 1289-1294.
- Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García. ASCIB: adaptive selection of cache indexing bits for removing conflict misses.. ISLPED : 51-56.
- Mario Lodde, José Flich, Manuel E. Acacio. Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support.. NOCS : 59-66.
- Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández. Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.. PDP : 221-228.
- Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio. Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.. SBAC-PAD : 43-50.
- Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García. Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.. PACT : 203-204.
- Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström. Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.. ICPP : 73-82.
- J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström. ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.. ICS : 53-62.
- Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström. The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.. IPDPS Workshops : 700-707.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs.. IPDPS : 893-905.
- Alberto Ros, Manuel E. Acacio, José M. García. A scalable organization for distributed directories.. J. Syst. Archit. : 77-87.
- Antonio Flores, Manuel E. Acacio, Juan L. Aragón. Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs.. J. Syst. Archit. : 429-441.
- Antonio Flores, Juan L. Aragón, Manuel E. Acacio. Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs.. IEEE Trans. Computers : 16-28.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats.. J. Supercomput. : 247-268.
- Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato. Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level.. IEEE Trans. Parallel Distributed Syst. : 1117-1131.
- Alberto Ros, Manuel E. Acacio, José M. García. A Direct Coherence Protocol for Many-Core Chip Multiprocessors.. IEEE Trans. Parallel Distributed Syst. : 1779-1792.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. Efficient and scalable barrier synchronization for many-core CMPs.. Conf. Computing Frontiers : 73-74.
- Alberto Ros, Manuel E. Acacio. Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs.. Euro-Par Workshops : 87-97.
- Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato. EMC 2 : Extending Magny-Cours coherence for large-scale servers.. HiPC : 1-10.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs.. ICPP : 267-276.
- Antonio Flores, Juan L. Aragón, Manuel E. Acacio. Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects.. PDP : 147-154.
- Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio. Characterizing Energy Consumption in Hardware Transactional Memory Systems.. SBAC-PAD : 9-16.
- Alberto Ros, Manuel E. Acacio, José M. García. Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.. APPT : 11-27.
- Epifanio Gaona-Ramírez, Juan Fernández, Manuel E. Acacio. Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades.. Euro-Par : 900-911.
- Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García. Distance-aware round-robin mapping for large NUCA caches.. HiPC : 79-88.
- J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco. Speculation-based conflict resolution in hardware transactional memory.. IPDPS : 1-12.
- Joaquín Franco, Gregorio Bernabé, Juan Fernández, Manuel E. Acacio. A Parallel Implementation of the 2D Wavelet Transform Using CUDA.. PDP : 111-118.
- Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, José M. García. Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors.. J. Parallel Distributed Comput. : 1413-1424.
- Antonio Flores, Juan L. Aragón, Manuel E. Acacio. An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.. J. Supercomput. : 341-364.
- Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato. Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.. IEEE Trans. Parallel Distributed Syst. : 1044-1056.
- Alberto Ros, Manuel E. Acacio, José M. García. Scalable Directory Organization for Tiled CMP Architectures.. CDES : 112-118.
- Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquín Franco. Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla.. CSC : 167-173.
- Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato. A fault-tolerant directory-based cache coherence protocol for CMP architectures.. DSN : 267-276.
- J. Rubén Titos Gil, Manuel E. Acacio, José M. García. Directory-Based Conflict Detection in Hardware Transactional Memory.. HiPC : 541-554.
- Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato. Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.. HiPC : 555-568.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades.. ICCS (1) : 456-465.
- Antonio Flores, Manuel E. Acacio, Juan L. Aragón. Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs.. ICPP : 295-303.
- Alberto Ros, Manuel E. Acacio, José M. García. DiCo-CMP: Efficient cache coherency in tiled CMP architectures.. IPDPS : 1-11.
- J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco. Characterization of Conflicts in Log-Based Transactional Memory (LogTM).. PDP : 30-37.
- José L. Abellán, Juan Fernández, Manuel E. Acacio. CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE.. PDP : 261-268.
- Gregorio Bernabé, Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José González. An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology.. Parallel Comput. : 54-72.
- Antonio Flores, Juan L. Aragón, Manuel E. Acacio. Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures.. AINA Workshops (1) : 752-757.
- Antonio Flores, Juan L. Aragón, Manuel E. Acacio. Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.. HiPC : 133-146.
- Alberto Ros, Manuel E. Acacio, José M. García. Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors.. HiPC : 147-160.
- Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato. A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.. HPCA : 157-168.
- Alberto Ros, Manuel E. Acacio, José M. García. An efficient cache design for scalable glueless shared-memory multiprocessors.. Conf. Computing Frontiers : 321-330.
- Francisco J. Villa, Manuel E. Acacio, José M. García. On the Evaluation of Dense Chip-Multiprocessor Architectures.. ICSAMOS : 21-27.
- Francisco J. Villa, Manuel E. Acacio, José M. García. Evaluating IA-32 web servers through simics: a practical experience.. J. Syst. Archit. : 251-264.
- Manuel E. Acacio, José González, José M. García, José Duato. A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors.. IEEE Trans. Parallel Distributed Syst. : 67-79.
- Alberto Ros, Manuel E. Acacio, José M. García. A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors.. Euro-Par : 582-591.
- Francisco J. Villa, Manuel E. Acacio, José M. García. Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.. HPCC : 213-222.
- Ricardo Fernández-Pascual, José M. García, Gregorio Bernabé, Manuel E. Acacio. Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures.. PDP : 76-83.
- Manuel E. Acacio, José González, José M. García, José Duato. An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration.. IEEE Trans. Parallel Distributed Syst. : 755-768.
- Francisco J. Villa, Manuel E. Acacio, José M. García. On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs.. International Conference on Computational Science : 541-544.
- Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel. MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing.. Future Gener. Comput. Syst. : 317-333.
- Manuel E. Acacio, José González, José M. García, José Duato. The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors.. IEEE PACT : 155-164.
- Manuel E. Acacio, José González, José M. García, José Duato. A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors.. IPDPS.
- Manuel E. Acacio, José González, José M. García, José Duato. Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.. PDP : 368-375.
- Manuel E. Acacio, José González, José M. García, José Duato. Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.. SC : 1:1-1:12.
- Manuel E. Acacio, José González, José M. García, José Duato. A New Scalable Directory Architecture for Large-Scale Multiprocessors.. HPCA : 97-106.
- Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel. An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet.. ACPC : 570-571.
- Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte. P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations.. IPPS/SPDP : 563-568.
- Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio. The Parallel EM Algorithm and its Applications in Computer Vision.. PDPTA : 571-578.
- Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel. A Performance Evaluation of P-EDR in Different Parallel Environments.. PDPTA : 744-750.
- Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte. The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations.. PDPTA : 1730-1736.
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Invited talks
- "Meltdown and Spectre Vulnerabilities: Causes, Risks and
Possible Solutions". Facultad de Informática, Universidad de
Murcia, Feb. 16th, 2018.
- “Increased Hardware Support for Efficient Communication and
Synchronization in Future Manycores”. Keynote at OMHI 2014,
August 26th, 2014.
- "Efficient Communication and Synchronization in Many-Core
CMPs". Dpto. Arquitectura de Computadores, Universidad de
Málaga, July 6th, 2012.
PHD STUDENTS
Current Students- Ismael Martínez Murcia (2031) “Enhanced Support for Asynchronous Memory Transfers in High-Performance GPU Architectures”. Co-advised with José L. Abellán.
- Jaime Martínez Fernández (2030) “Near Data Processing in GPUs to Accelerate Emerging Workloads”. Co-advised with José L. Abellán.
- Germán Vicente Tomás (2030) “Memory System Organization for Multi-chiplet GPUs”. Co-advised with José L. Abellán.
- Joaquín Ferrer Calderón (2029) “Efficient Communication and Synchronization in Manycores”. Co-advised with Ricardo Fernández-Pascual.
- Pascual Abellán Navarro (2028) “Efficient Organizations of the Branch Target Buffer in Processors for Data Center Servers”. Co-advised with Alberto Ros and Josué Feliu (UPV).
- Adrián Fenollar Navarro (2028) “Inference Accelerator Architectures for the Edge”. Co-advised with José L. Abellán.
- Nicolás Meseguer Iborra (2027) “Efficient, High-Performance Memory System for GPU Architectures”. Co-advised with José L. Abellán.
- Francisco Muñoz-Martínez. December 2022. “Hardware Techniques for the Design of Efficient Inference Accelerators of Deep Neural Networks”. Co-advised with José L. Abellán.
- Epifanio Gaona. January 2016. "Efficient Hardware Transactional Memory Systems". Co-advised with Juan Fernández.
- José L. Abellán. December 2012. "Efficient Communication and Synchronization in Many-Core CMPs". Co-advised with Juan Fernández.
- Rubén Titos-Gil. Ph.D. November 2011. "Hardware Techniques for High-Performance Transactional Memory in Many-Core Chip Multiprocessors".
- Antonio Flores. Ph.D. September 2010, "Improving the Performance and Reducing the Consumption of Multicore Processors using Heterogeneous Networks". Co-advised with Juan L. Aragón.
- Alberto Ros, Ph.D. September 2009, "Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors" (co-advised with José M. García).
- Ricardo Fernández-Pascual, Ph.D. July 2009, "Fault-tolerant cache coherence protocols for CMPs" (co-advised with José M. García).
PhD thesis
Title: “Improving the Performance and Scalability of Directory-based Shared-Memory Multiprocessors”Author: Manuel E. Acacio
Advisors: José Duato (UPV), José Manuel García (UM) and José González (Intel Barcelona Labs)
Defended on March 26, 2003
Awarded with the Best Ph.D. Thesis Prize. Facultad de Informática. Universidad de Murcia. January 2004.