Research Internships
DUAL CONSISTENCY STORE BUFFER FOR OUT OF ORDER PROCESSORS (MS Thesis)
Apr 2019 – Dec 2019
Murcia, Spain
The Store Buffer (SB), designed to ensure the inorder retirement of stores is essential for guaranteeing the Total Store Order (TSO) memory model. However, a cache miss of the leading store blocks all subsequent stores, which incurs a severe performance bottleneck. We present a solution to this problem by allowing stores to be shuffled within safe regions, such that fast stores can bypass long latency ones while providing the same observable behavior as TSO. The safe regions (i.e. within which stores can be safely reordered) are marked by the compiler. To leverage this information, we design a new dual-mode store buffer that switches between the in-order and out-of-order retirement of stores within the unsafe and respectively safe regions. Correctness is preserved through well-placed fences inserted by the compiler to delineate the regions, which impede the retirement of stores from the following regions until all stores of the current region complete. The regional out-of-order execution of stores significantly decreases stall cycles and brings 8% performance improvements compared to the state-of-the-art, with only one extra bit per entry in the dual-mode store buffer.
Adding support of xDRF in SNIPER simulator
Jul 2018 – Oct 2018
Uppsala, Sweden
The work include understanding the structure of xDRF compiler and adding support for SNIPER Simulator inorder to generate traces. GEMS simulator was also modified to read special information put by compilers. The information represents weather a store can be reordered or not. We designed a special store buffer which can process all compiler information and allow stores to perform inorder and out of order according to the information passed by the compiler.
Generation Of HDL Codes Of Different Image Processing Algorithms And Efficient DCT Architecture Using MATLAB HDL Coder
May 2016 – July 2016
Varanasi, India
The work include understanding the structure of xDRF compiler and adding support for SNIPER Simulator inorder to generate traces. GEMS simulator was also modified to read special information put by compilers. The information represents weather a store can be reordered or not. We designed a special store buffer which can process all compiler information and allow stores to perform inorder and out of order according to the information passed by the compiler.