[2024] [TO APPEAR] Sawan Singh, Arthur Perais, Alexandra Jimborean, and Alberto Ros. Alternate Path µ-op Cache Prefetching in 51st Annual International Symposium on Computer Architecture (ISCA‘51), Buenos Aires, Argentina. DOI PDF Slides
[2023] Sawan Singh, Josue Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions in 32nd IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT‘32), Vienna, Austria. DOI PDF Slides
[2022] Sawan Singh, Arthur Perais, Alexandra Jimborean, and Alberto Ros. Exploring Instruction Fusion Opportunities in General Purpose Processors. In Proceedings of the 55th International Symposium on Microarchitecture (MICRO‘55), Chicago, USA. DOI PDF Slides
[2020] Sawan Singh, Alexandra Jimborean, and Alberto Ros. Regional Out-of-Order Writes in Total Store Order. In Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques (PACT‘30). Association for Computing Machinery, New York, NY, USA, 205–216. DOI PDF Slides Video
[2019] Sawan Singh, Alberto Ros, Guido Masera. DUAL CONSISTENCY STORE BUFFER FOR OUT OF ORDER PROCESSORS. MS Thesis, Politecnico Di Torino, Italy. PDF
[2016] Sawan Singh. HDL Code Generation Of Efficient DCT Architecture Using MATLAB HDL Coder. International Journal of Innovative Research in Computer and Communication Engineering. PDF