"A Complexity-Effective Local Delta Prefetcher". Agustín Navarro-Torres, Biswabandan Panda, J. Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals-Yúfera, and Alberto Ros. IEEE Transactions on Computers (IEEE TC). 2024. JCR 2024: Q2. [IEEE] [PDF]
"Secure Prefetching for Secure Cache Systems". Sumon Nath, Agustín Navarro-Torres, Biswabandan Panda, and Alberto Ros. 57th ACM/IEEE International Conference on Microarchitecture (MICRO 2024). 2024. GGS A [IEEE] [PDF]
"BALANCER: Bandwidth Allocation and Cache Partitioning for Multicore Processors". Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Víctor Viñals-Yúfera The Journal of Supercomputing. 2023. JCR 2023: Q2 [SpringerLink] [PDF] [Repository]
"Berti: an Accurate Local-Delta Data Prefetcher." Agustín Navarro-Torres, Biswabandan Panda, J. Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals-Yúfera, and Alberto Ros. 55th ACM/IEEE International Conference on Microarchitecture (MICRO 2022). 2022. GGS A. [IEEE Xplore] [PDF] [Slides] [Repository] [ChampSim]
"Synchronization Strategies on Many-Core SMT Systems" Agustín Navarro-Torres, Maria Carpen-Amarie, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2021). 2021. CORE: B. [IEE Xplore] [PDF] [Slides] [Repository]
"Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP" Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Víctor Viñals-Yúfera. PLOS ONE. 2019. JCR 2018: Q2. [PDF] [Repository]
"Exposing Abstraction-Level Interactions with a Parallel Ray Tracer". Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique Torres, Pedro Álvarez, Pablo Ibáñez, and Víctor Viñals Workshop on Computer Architecture Education (WCAE).2 2019. [PDF] [SLIDES]
"Memory Hierarchy Performance Characterization of SPEC CPU2017". Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Víctor Viñals-Yúfera Student Poster Session of the 14th Conference on High Performance and Embedded Architectures and Compilers [PDF] [POSTER]
Ph.D Thesis: Contributions to High-Performance Memory Hierarchies: Program Characterization, Resource
Control, Transactional Synchronization, and Hardware Prefetching
Sobresaliente Cum Laude. Mención Doctorado Internacional. 17-abr-2023
Advisors: Pablo Ibáñez Marín & Jesús Alastruey-Benedé
[PDF][SLIDES]
Internship: Hardware Prefetching
Supervisor: Alberto Ros
1/Sept./2021 - 28/Dec./2021
Universidad de Murcia, Murcia, Spain
Internship: Concurrent Scalable Systems
Supervisor: Maria Carpe-Amarie
1/Sept./2020 - 28/Feb./2021
Huawei Research Center, Zurich, Switzerland